System-on-Chip for Real-Time Applications

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Wael Badawy, Graham A. Julien
Springer Science & Business Media, Oct 31, 2002 - Technology & Engineering - 456 pages
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System-on-Chip for Real-Time Applications will be of interest to engineers, both in industry and academia, working in the area of SoC VLSI design and application. It will also be useful to graduate and undergraduate students in electrical and computer engineering and computer science.
A selected set of papers from the 2nd International Workshop on Real-Time Applications were used to form the basis of this book. It is organized into the following chapters:

-Introduction;
-Design Reuse;
-Modeling;
-Architecture;
-Design Techniques;
-Memory;
-Circuits;
-Low Power;
-Interconnect and Technology;
-MEMS.

System-on-Chip for Real-Time Applications contains many signal processing applications and will be of particular interest to those working in that community.
 

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Contents

INTRODUCTION
1
The Challenge and Opportunities
3
Electronic Product Innovation Using Direct Mapped Signal Processing SoC Cores
17
SYSTEMONCHIP IMPLEMENTATION OF SIGNAL PROCESSORS
26
DESIGN REUSE
29
Methodologies and Strategies for Effective Design Reuse
31
A VHDLSystemC Comparison in Handling Design Reuse
41
Aspect partitioning for Hardware Verification Reuse
51
Survey of Emerging Nonvolatile Embedded Memory Technologies The Challenge
227
Configurable Parallel Memory Implementation For SystemonChip Designs
237
XORscheme Implementations In Configurable Parallel Memory
249
An Novel Low Power Embedded Memory Architecture for MPEG4 Applications with Mobile Devices
262
Assessment of MPEG4 VTC and JPEG2000 Dynamic Memory Requirements
273
CIRCUIT TECHNIQUES
285
Modified Distributed Arithmetic Architecture for Adiabatic DSP Systems
287
Design of a CMOS Wide Range Logarithmic Amplifier with a Modified Parallel Architecture
296

Reconfigurable Combinatorial Accelerators for Real Time Processing
61
Tuning Methodologies for Parameterized Systems Design
71
TEST AND VERIFICATION
83
Formal Verifications of Systems on Chips Current and Future Directions
85
A Practical Approach to the Formal Verification of SoCs with Symbolic ModelChecking
98
High Performance Verification Solutions for SOC Designs
111
Novel Test Methodologies for SoCIP Design Implementation and Comparison
125
MODELING
137
SOC Modeling and Simulation Based on Java
139
RTOS Modeling Using SystemC
150
Modeling Synthesis and Implementation of Communicating Hierarchical FSM
160
A Modeling Method for Reconfigurable Architectures
170
DESIGN TECHNIQUES
181
The SyslibPicasso Methodology for the CoDesign Specification Capture Phase
183
AUTOMATIC PORTING OF BINARY FILE DESCRIPTOR LIBRARY
193
Code Compression on Transport Triggered Architectures
203
AN APPROACH TO FLEXIBLE MULTILEVEL NETWORK DESIGN
214
MEMORY
225
Digital Hardware Implementation OF Continuous And Discrete Chaotic Generators
305
Novel 1bit Full Adder Cells for LowPower System OnChip Applications
314
LOW POWER
325
A New Logic Design Method for Considering Low Power and High Testability
327
System Synthesis for OpticallyConnected Multiprocessors OnChip
339
Low Power SystemonChip Platform Architecture for High Performance Applications
349
INTERCONNECT TECHNOLOGY
357
SoC Interconnect in Deep Submicron
359
Optimizing Inductive Interconnect for Low Power
380
Skin Effects in System on a Chip Interconnects
392
MicroElectroMechanical Systems
403
Road Map Towards Designing MEMS Devices With HighReliability
405
A MEMS SOCKET INTERFACE FOR SOC CONNECTIVITY
411
On the Application of Finite Element to Investigate the Reliability of Electrostatic CombDrive Actuators Utilized in Microfluidic and Space systems
422
AN HDL MODEL FOR A VACUUMSEALED MICROMACHINED PRESSURE SENSOR
429
Performance Analysis of MEMSbased Inertial Sensors for Positioning Applications
440
Index
451
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