HPCA: The Seventh International Symposium on High-Performance Computer Architecture : Proceedings, 19-24 January 2001, Monterrey, Nuevo Leon, México
IEEE Computer Society, 2001 - Computers - 318 pages
Topics covered in this text include: microarchitecture; memory architectures; multiprocessor systems; code generation techniques; energy and thermal management; prediction techniques; application-specific designs; performance modelling and analysis; and latency tolerance techniques.
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Custom Microarchitecture for the Stack
Register Renaming and Scheduling for Dynamic Execution of Predicated
DataFlow Prescheduling for Large Instruction Windows in OutofOrder
23 other sections not shown
algorithm allocation Annual International Symposium applications array average bandwidth benchmarks BHGP bits block branch predictor Bzip2 cache lines cache misses CGHC channel cluster co-processor compiler compressed Computer Architecture configuration critical path cycles database DDMT DFCM DRI i-cache dynamic entry evaluate execution fetch Figure function hardware IEEE impact implementation increase input instructions issue buffer L2 cache latency leakage energy load mapping memory system Microarchitecture misprediction miss rate module multiprocessor node optimization overhead P.host P.mem packet perceptron performance physical pipeline prediction prefetch prescheduler Proc processor profiling Rambus reduce register allocation register renaming renaming resizing router scheduling scheme Section sharing code shows simulation simultaneous multithreading snoop speedups stack static superpages superscalar switch Symposium on Computer techniques thread threshold throughput tion TLB miss TPC-W trigger virtual address virtual-channel router VLIW workloads