Performance Evaluation of a Multiple Function-unit Processor |
Common terms and phrases
arithmetic or Boolean Boolean instruction Bowra and Torng branch instruction busy bit capable of executing CDC 6600 system clock period common data busing Common-Data-Busing Implementation Scheme constraints copy of fu Data Flow dissertation Example 2.1 executing the instruction finishes its execution Flag and Tag flag tag Flow Chart free copy func gate delays Hard-Wired Control Unit independent probability instruction issue policy issuance Issuance-of-an-Instruction Istanbul Listed in 3.1 load-register instruction minor cycles MULTIPLE FUNCTION-UNIT PROCESSOR number of function operand register previous instruction previous study 1,2 previously issued instruction primary memory probability of occurrence processor operation program structure purpose register ready for issue register transfers release signal requires the result result register Result-Queuing Implementation Scheme second operand SOFTWARE STRUCTURES specified as follows stores the result T(ex tag number Tag Registers Associated tion unit ελ