16-/32-bit Embedded Processor Handbook |
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Contents
376TM EMBEDDED PROCESSOR | 3-1 |
FAMILY | 3-3 |
MEMORIES AND PERIPHERALS | 6-1 |
2 other sections not shown
Common terms and phrases
80960 architecture active addressing modes AP-Bus asserted buffers burst Bus Controller bus cycle bus master byte enables byte or word cache Capacitance chip select CHMOS CLK2 CLKOUT clock cycle command configured control block control registers coprocessor deasserted debug device disp DMA channel DMA controller DMA transfer DT/R EPROM execution external fault float frame functions hardware HLDA HOLD HOLDA Inactive indicates input integer Intel interface internal interrupt controller interrupt request interrupt sources interrupt vectors L-Bus latched load LOCK logic Low insertion force MAX COUNT register memory module Non-Maskable Interrupt offset on-chip Opcode open-drain operands operation output Package performance peripheral Pin Grid Array pointer PQFP priority procedure provides READY register set register/memory RESET segment Setup specific stack STATUS REGISTER synchronized Table TCLCL timer types Valid Delay Voltage wait WAVEFORMS zero