Computer Architecture: Pipelined and Parallel Processor DesignComputer Architecture: Pipeline and Parallel Processor Design was designed for a graduate level course on computer architecture and organization. The book's content, especially the last half of the book, represents the most advanced material that a typical graduate student studies before directly encountering the design process. The text avoids extensive compendiums of current features of various processors or technologies, just as it stresses concepts that underlie these processor designs. It abstracts the essential elements of processor design and emphasizes a design methodology including: design concepts, design target data, and evaluation tools, especially those using basic probability theory and simple queuing theory. |
Contents
Architecture and Machines | 1 |
Concurrent Processors | 7 |
Shared Memory Multiprocessors | 8 |
7 | 132 |
Pipelined Processor Design | 181 |
1 | 265 |
54 | 336 |
Memory System Design | 345 |
Processor Studies | 663 |
Appendix A DTMR Cache Miss Rates | 719 |
New DRAM Technologies | 747 |
Appendix F Some Details on BusBased Protocols | 755 |
| 765 | |
| 782 | |
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Common terms and phrases
allocation assume bandwidth bits branch prediction buffer bypass bytes cache access cache miss CBWA chapter chip clock code density complete compute condition code conditional branch cost cycle cycles per instruction data cache decimal decode delay dependency DF DF DF EX disk distribution DTMR dynamic effect entry environment EX EX example fetch Figure floating-point format I-buffer I-cache implementation in-line instruction execution instruction set integer interlock L/S architecture M-ratio machine memory system microprocessor MIPS miss rate multiple multiprocessor node number of instructions operand operating system overhead path penalty pipelined processor prefetch processor design protocols queue references register set register windows relative request rate result RISC run-on segment sequence server set associative simple speedup storage struction Table template tion traffic vector processor write
Popular passages
Page 765 - RH Katz, SJ Eggers, DA Wood, CL Perkins, and RG Sheldon. Implementing a cache consistency protocol.
Page 773 - Two-level adaptive training branch prediction," in Proceedings of the 24th Annual International Symposium on Microarchitecture, pp. 51-61, November 1991. [12] JR Allen, K. Kennedy, C. Porterfield, and J. Warren, "Conversion of control dependence to data dependence," in Proceedings of the 10th ACM Symposium on Principles of Programming Languages, pp.
References to this book
Integrated Circuit and System Design. Power and Timing Modeling ... Jorge Juan Chico,Enrico Macii No preview available - 2003 |