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### Contents

A PAlgebraic Extension of Post Algebras of Order w+ | 4 |

Ternary Logic Based on a Novel MOS Building Block Circuit | 20 |

LowPower Dissipation MVL Integrated Circuits for VLSI MOS Technologies | 33 |

Copyright | |

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### Common terms and phrases

4-valued adder algebras of order algorithm array basic binary logic binary threshold functions Boolean cell charge-coupled devices clause CMOS column complex Computer corresponding current-mode decoder defined denotes detector devices elements example expert system Figure finite func function f functions realized fuzzy Fuzzy Logic gate GF(q given IEEE implementation input ISMVL latin square Lemma LFSR linear literals Liu Yunfeng logic circuits logic values minimal minterms MODSUM monotone-increasing multi-valued multi-valued logic multiple-valued logic multiplication n-ary NMOS obtained operation optical output encoding pan-valid pass transistor permutation PLA's polynomial Post algebras predicate Proc product terms Proof radix reference patterns regular ternary logic representation represented shown in Fig signals simulation staircase functions switching t-norm ternary logic functions ternary majority functions Theorem threshold voltage tion Trans transistors truth tables Type 2 PLA unary functions variables vector VLSI