Cost-effective Processor Design with an Application to Fast Fourier Transform ComputersA cost-effective processor design is one that attains a high ratio of processing performance to processor component cost. This research investigates the circuit design of a processor or processing subsystems for costeffective implementation of a particular computation algorithm. The logic designs considered in this work use circuit components for which the delay and cost of functional building blocks or gates are known. A logic design technique is described that permits processing performance and cost comparisons among alternative computation algorithms and circuit technologies. It also provides a basis for contrasting alternative processor architectures, including both pipelined and parallel computing structures. (Modified author abstract). |
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COSTEFFECTIVE PROCESSOR DESIGN | 13 |
COSTEFFECTIVE DESIGN OF FAST FOURIER TRANSFORM | 49 |
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adder modules ALU WITH LAC arithmetic modules attained Attn balanced cordic bit-widths bottleneck segment calculation carry-save adder cascade by replication cascade segment circuit design circuit implementation circuit modules circuit technologies component cost computation algorithm computation elements computational sequence cost-effective design cut set design goals design results design value digital filters elementary results factors Fast Fourier Transform FFT algorithm full-butterfly Hanscom Field implementation value input Kalman filter KBTLNK KOPT maximum maximum-performance design maximum-value design maximum-value implementation MSI fast adder multiplexed nonpipelined number of pipeline operand parallel replication parameters PERF performance and cost performance bottleneck performance capability performance per unit pipeline stages pipelined cascade architecture processing architectures processing band processing bandwidth processing performance radix-2 register cost register modules relative Schottky ALU selected shown in Figure simple architecture simple element simple-element standard D-type standard half-butterfly standard latch Standard MSI fast subelement SUBROUTINE TAUHAT tion utilized