Digital Signal Processing with Field Programmable Gate ArraysField-Programmable Gate Arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Novel FPGA families are replacing ASICs and PDSPs for front end digital signal processing algorithms more and more. The efficient implementation of these algorithms is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 30 design examples. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, and advanced algorithms with high future potential. Each chapter contains exercises. The VERILOG source code and a glossary are given in the appendices. The accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Baseline" software. "5 Stars: this book is well written and covers many of the aspects of DSP with FPGAs. I run a business that specializes exclusively in high performance DSP designs using FPGAs. This book pretty much covers it all, in fact it closely parallels the material we present in our DSP for FPGAs seminar. I very highly recommend this book." Ray Andraka of Andraka Consultants, N. Kingstown, RI |
Contents
1 | |
Exercises | 25 |
Computer Arithmetic | 29 |
Infinite Impulse Response IIR Digital Filters | 115 |
Time Domain Interleaving | 131 |
Exercises | 141 |
Fourier Transforms | 209 |
Common terms and phrases
1pm_add_sub aclr adder aload Altera array aset assign Author-EMAIL bit width blocks CIC filter CLBs clk_div2 clk2 clock clock(clk coefficients compiler complex component compute convolution CORDIC decimation decoder defparam device Digital Filters Digital Signal Processing DOWNTO END PROCESS example factor filter bank FIR filter flex Fourier Transform FPGA frequency halfband filter IEEE IEEE Transactions ieee.std_logic_1164.ALL ieee.std_logic_arith.ALL implementation impulse response input integer INTEGER RANGE Kaiser window length LFSR LIBRARY ieee linear-phase logic Logic Synthesis LOOP LPM_WIDTH LSBs matrix MaxPlusII module MSBs multiplier N₁ output parameter passband PDSPs polynomial polyphase PORT posedge clk primitive polynomials recursive Registered Performance result S-boxes sampling sequence shown in Fig Signal Processing simulation sload speed sset STD_LOGIC STD_LOGIC_VECTOR synthesis Table table_in table_out table0out01 transfer function two's complement Verilog VHDL WAIT UNTIL clk wavelet Winograd x_in Xilinx y_out zero