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abraded abrasion aluminum aluminum sidewalls analysis annealing anticorrosion treatments bond pad burn-in carbon black chemical chemical equilibrium chlorine CMP process coated substrate corrosion corrosion defects decreases degradation deposited device dielectric diffusion coefficients dispersion dissolution rate distribution Electrochem electromigration electron energy analyzer etch process etch rate experimental failure Figure flood gun gate oxide gelatin hot carrier hydrogen increase interconnect interface layer material measured mechanism metal etch metal lines metal stack MOCVD multilayers nanolaminate NH4OH nitride nm/min oxide etch oxide films oxygen parameters particles passivation peak PECVD performance photoresist plasma plasma etching polarization curves poly-Si polyelectrolyte polyimide potential reaction reliability removal rinse sample scem sheet resistance shown in Fig shows silicon SiO2 film slurry solution spectra spectroscopy sputtered substrate surface temperature test structures thickness TiN coatings voltage wafers WDXRF Weibull distribution X-ray photoelectron spectroscopy
Page 135 - Planarization by Chemical-Mechanical Polishing for Multilevel Metal Integrated Circuits', O'Mara & Associates, Palo Alto, p. 1. 3. KC Cadien and DA Feller, US Patent 5,516,346, 1996. 4. FB Kaufman, DB Thompson, RE Broadie, MA Jaso, WL Guthrie, DJ Pearson and MB Small, J. Electrochem. Soc., 1991, 138, 3460.
Page 20 - ... Texas Instruments, Inc., M/S 374 13353 Floyd Road, Dallas, Texas 75243 Kenichi Nakata Texas Instruments Japan Limited 2350 Kihara Mihomura Inashikigun ibaraki-ken, Japan ABSTRACT The die size has been shrunk dramatically in the past few years and the requirements for transistor performance also is increased. Therefore, the silicon substrate damage during the plasma etch has become an important issue in current ULSI fabrication. Many transistor parameters are affected by Si damages such as the...
Page 135 - Soc., 138, 3460 (1991). 4. JM Steigerwald, A Fundamental Study of Chemical Mechanical Polishing of Copper Thin Films, Ph.D. Dissertation, Rensselaer Polytechnic Institute, (May 1995).
Page 233 - ZJ Ma, JC Chen, ZH Liu, JT Krick, YC Cheng, C. Hu, and PK Ko, "Suppression of boron penetration in p+polysilicon gate p-MOSFET,S using low temperature gate-oxide N2O anneal", IEEE Electron Dev.
Page 20 - SILICON DAMAGE MECHANISM IN OXIDE ETCH Ming Yang Texas Instruments, Inc., M/S 374 13353 Floyd Road, Dallas, Texas 75243 Kenichi Nakata Texas Instruments Japan Limited 2350 Kihara Mihomura Inashikigun ibaraki-ken, Japan ABSTRACT The die size has been shrunk dramatically in the past few years and the requirements for transistor performance also is increased. Therefore, the silicon substrate damage during the plasma etch has become an important issue in current ULSI fabrication. Many transistor parameters...
Page 20 - ... mechanism for such oxide etch and also will present the study of such silicon damage by using Secondary Ion Mass Spectroscopy (SIMS), Minority Carrier Life Time test (MCLT) and Transmission Electron Microscopy (TEM). All the experimental results strongly support the silicon damage mechanism what we proposed here. INTRODUCTION Plasma etching has become the most important technique for pattern transfer as device dimensions are scaled down to submicrometer range and even more important to quarter...
Page 22 - ... should remember that during this etch process some of Si substrate area have been exposed to the plasma. Due to the chemical activity of the Si dangling bonds at the Si surface and it is very possible for the ionized oxygen released from the oxide etch reaction adsorb on certain active sites of the Si surface to locally oxidize the Si. If it is true then it is very obvious that those locally oxidized areas will be etched by the F as indicated in reaction (1). Since this etch process has high...
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