Data Communication Systems and Their Performance: Proceedings of the IFIP TC6 Fourth International Conference on Data Communication Systems and Their Performance, Barcelona, Spain, 20-22 June, 1990G. Pujolle, R. Puigjaner The research papers in this volume describe recent, original developments in techniques, tools and applications in the area of communication system performance. Involved in the project are researchers from the world's leading universities, research institutes and companies. |
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Page 207
... A - Bus is stored into the j - th FIFO . The cell in the MBR is stored into the SBM at the address on the A - Bus , and the address is stored into the FIFO buffer which is open for writing by the DAD . If the input register ( IDRI ) of ...
... A - Bus is stored into the j - th FIFO . The cell in the MBR is stored into the SBM at the address on the A - Bus , and the address is stored into the FIFO buffer which is open for writing by the DAD . If the input register ( IDRI ) of ...
Page 209
... of the BMBR1 is stored into the MEM1 at the address on the A - Bus . At the same time , the content of the memory data register ( BMBR2 ) of the MEM2 is also stored into the MEM2 at the address in the memory address register BMAR ...
... of the BMBR1 is stored into the MEM1 at the address on the A - Bus . At the same time , the content of the memory data register ( BMBR2 ) of the MEM2 is also stored into the MEM2 at the address in the memory address register BMAR ...
Page 210
... A - Bus and BMAR . • SBM [ A - Bus ] → MBR , The oldest address stored in FIFO i → FR i if any , • An address in the IAF → IDRO if necessary , • MEM1 [ A - Bus ] → BMBR1 , and • MEM2 [ BMAR A - Bus ] → BMBR2 . = • Send the cell in ...
... A - Bus and BMAR . • SBM [ A - Bus ] → MBR , The oldest address stored in FIFO i → FR i if any , • An address in the IAF → IDRO if necessary , • MEM1 [ A - Bus ] → BMBR1 , and • MEM2 [ BMAR A - Bus ] → BMBR2 . = • Send the cell in ...
Contents
Performance Issues of the DQDB Protocol | 3 |
WORKLOAD | 20 |
Applications of Sample Path to Communication Networks Control | 23 |
Copyright | |
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access control algorithm analysis approximation arcs ARQ protocols arrival process assigned assumed average bandwidth bit rate buffer overflow bursty bytes cell stream channel child stations Computer consider cycle D-Bus D-channel Data Communication Systems defined denote destination DQDB equation error evaluation exponentially distributed FDDI FIFO Figure function geometric distribution given INFOCOM input port input queue ISDN load Markov chain maximum mean measurement monitoring node np-customers number of packets obtained optimal output port output queue packet arrival packet delay packet switch parameters Poisson process priority probability generating function Proc proposed response scheme queue length queueing system random variables Router sample path Science Publishers B.V. server simulation slot statistical multiplexer Stochastic subscriber circuits throughput token Token Ring traffic matrix traffic network transfer transit trunk transmission transmitted virtual circuit waiting Θ Θ