Proceedings: 11th International Symposium on System Synthesis : December 2-4, 1998, Hsinchu, Taiwan, ROCThis is a collection of papers presented at the 11th International Symposium on System Synthesis. It covers topics such as: code generation; optimization issues; application-specific synthesis techniques; synchronization and interface issues; instruction encoding; and software synthesis techniques. |
Contents
A Uniform Optimization Technique for Offset Assignment Problems | 3 |
Code Generation for Compiled BitTrue Simulation of DSP Applications | 9 |
Addressing Optimization for Loop Execution Targeting DSP with AutoIncrementDecrement Architecture | 15 |
Copyright | |
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Common terms and phrases
access graph address register allocation application approach architecture ASIA-II behavior bit-true channel circuit clock cycle code sharing codesign communication communication protocols compiler components Computer constraints core cost data list data ordering datapath decoder delay Differential Evolution driver DTSE edge eDRAM embedded DRAM embedded systems encoding estimation example execution false path FPGA functional unit global hardware heuristic hierarchical high-level synthesis IEEE immediate values implementation input interface iteration latch latency LD-CELP logic loop mapping memory meta flow method methodology microcontroller modules node offset assignment opcode operations optimization overhead parameters partitioning performance probability Proc procedure processor protocol register allocation resource retargetable retargetable compilation retiming scheduling algorithm sharing shown in Figure signal simulation solution specification stage step subtask superscalar target task techniques tion tool variables VHDL VLIW VLSI width