IEEE VLSI Test SymposiumIEEE Computer Society, 2000 - Application-specific integrated circuits |
Contents
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set | 15 |
Low Power BIST via Nonlinear Hybrid Cellular Automata | 29 |
Silicononinsulator Technology Impacts on SRAM Testing | 43 |
Copyright | |
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Common terms and phrases
adder algorithm analog analog circuits analysis applied architecture at-speed ATPG behavior bits Built-In Self-Test chip circuit clock CMOS column compactor Computer constraints core cycles detected devices diagnosis error experimental results fault coverage fault model fault secure fault simulation fault test fault-free FFMs flip-flop frequency functional gate gate-level Golomb coding hardware IDDQ testing IEEE implementation input interconnect International Test Conference jitter latches LBIST LFSR linear logic logic value measurements memory method methodology modules multipaths node number of test on-chip operation optimal output parameters path delay fault performed phase Proc procedure propagation proposed pseudo-random random scan cells scan chain scheme Section selected self-test sequential circuits shown in Figure SIFAR signal signature stuck-at fault synthesis Table technique Test Conf test cubes test data test patterns test points test sequence test set test vectors testable tester tion transistor transition VHDL virtual scan VLSI voltage