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Application and Validation of PLL Behavioral Models
Poster and Vendor Exhibits
Behavioral Model Based DesignOptimization 1
admittance AE modulator algorithm analog circuits approach architecture baseband behavioral models Boolean BSMOR capacitance capacitor carrier channel Circuits and Systems clock CMOS coefficient complex components computed coupling CPPLL DDD graphs density device diagram effects electron environment equations FPGA frequency function hardware description language hierarchical histogram IEEE IEEE Trans implementation inductor injection input Integrated Circuits interconnect interface jitter language linear logic loop filter macromodel method methodology mixed-signal Modelica Modeling and Simulation node nonlinear operation optimization oscillator output Paragon parameters parasitic performance phase Phase-Locked Loops port product term proposed reduced block RFID sampling schematic shown in Figure shows signal simulation results Simulink structure substrate contact substrate noise supply voltage switch symbolic analysis synthesis System Verilog transceiver transistor transistor level transmitter variables verification Verilog Verilog-A VHDL VHDL-AMS voltage waveform