Microcomputer Systems: The 8086/8088 Family : Architecture, Programming, and Design |
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ADDR address bus addressing modes arithmetic array ASCII assumed binary bits block bus control logic bus cycle bus master byte called channel character clock command contents control register coprocessor count counter data bus decoder defined digit DISP-HI display DMA controller error executed Figure flags format given in Fig hexadecimal high-order indicates initialization input integer Intel Intel Corporation interface interrupt request interrupt routine intersegment latches Load local descriptor table loop low-order macro maximum mode memory operand MOV AX MOV MOV offset operand operation output parameter pointer port priority procedure processor program sequence PUSH queue RESET result segment address segment register shown in Fig signal source module stack status register stored string sync characters system bus terminal transfer unpacked BCD variable word write