IEEE VLSI Test SymposiumIEEE Computer Society, 2001 - Application-specific integrated circuits |
Contents
Compression Technique for Interactive BIST Application | 9 |
Robust and LowCost BIST Architectures for Sequential Fault Testing | 15 |
Diagnosis Methods | 21 |
Copyright | |
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Common terms and phrases
abstract algorithm analysis applied approach architecture at-speed ATPG benchmark circuits bijection bits capacitances cell chip clock CMOS CMOS latch column compression Computer Computer-Aided Design crosstalk crosstalk defect cycle cycle-to-cycle period jitter defect coverage delay faults detect diagnosis dominator gate DSM error model encoding equivalent experimental results fanout fault coverage fault effects fault models fault pairs fault simulation flip-flop flops frequency function Golomb codes ground bounce IDDQ IEEE IEEE Trans implementation International Test Conference IP cores LFSR logic march tests measurement memory method methodology minvdd module node overshoot path primary input primary outputs Proc propagation proposed random resistive opens sampling scan chains scheme Section self-test sequence sequential circuits shown in Figure shows signal stuck-at fault system-on-a-chip Table technique Test Conf test length test patterns test set test vectors testability tester tion transistor transition VLSI voltage