Microprocessors, Volume 2

Front Cover
Intel Corporation, 1992 - Intel 80386 (Microprocessor)

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Contents

PIN ASSIGNMENT
4-4
REAL MODE ARCHITECTURE 431
4-31
FUNCTIONAL DATA 460
4-60
Copyright

13 other sections not shown

Common terms and phrases

240 Tri Tri 386 DX Microprocessor A.C. Specifications active LOW Addr address bus Address Mode asserted breakpoint buffer byte Cache Directory Capacitive Load pF Chip Select configured CPUCLK2 data bus decoding device DRAM DRAMRDY drive DX CPU DX MCP enabled execution Figure Float Global Descriptor Table High HLDA Hold Drv Hold Hold from CAS Inactive indicates input instruction INTEL INTEL CORPORATION Intel386 DX Intel386 SL CPU Intel386 SX Microprocessor interface interrupt IOCHRDY ISA bus ISACLK2 Line Fill linear address LOCK Mode F1 Mode non-pipelined Note ns SF opcode operand operation Parameter PEREQ pipelined PQFP privilege level processor Protected Mode PSTART PU Tri Pulse Width read cycles READY READYO Real Mode refresh Register/Memory request RESET Segment Register selector SL SuperSet SRAM SRDY SYSCLK System Bus Valid Delay Virtual 8086 Mode write cycle Write Data

Bibliographic information

TitleMicroprocessors, Volume 2
Microprocessors, Intel Corporation
ContributorIntel Corporation
PublisherIntel Corporation, 1992
Original fromthe University of Michigan
DigitizedJul 25, 2011
ISBN1555121500, 9781555121501
  
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