Proceedings, International Test Conference 1995 |
From inside the book
Results 1-3 of 82
Page 191
... technique for MCMs . The proposed test technique involves a single ended conventional probe and test fre- quency of ~ 700 MHz . The probe incorporates a tuned load in which the passive elements are easily realized with cur- rent ...
... technique for MCMs . The proposed test technique involves a single ended conventional probe and test fre- quency of ~ 700 MHz . The probe incorporates a tuned load in which the passive elements are easily realized with cur- rent ...
Page 293
... technique were not applied ? If the answer is ' no ' , then the technique is classifed as DFT . For example , both full and partial scan designs are DFT techniques . On the other hand , redundancy removal techniques are SFT techniques ...
... technique were not applied ? If the answer is ' no ' , then the technique is classifed as DFT . For example , both full and partial scan designs are DFT techniques . On the other hand , redundancy removal techniques are SFT techniques ...
Page 423
... technique satisfies all these requirements , and no single DFT technique is likely to do so . In this paper , we propose combining several DFT techniques to satisfy the above requirements . In particular , our approach mixes partial ...
... technique satisfies all these requirements , and no single DFT technique is likely to do so . In this paper , we propose combining several DFT techniques to satisfy the above requirements . In particular , our approach mixes partial ...
Contents
Welcoming Message | 1 |
Technical Papers Evaluation and Selection Process | 8 |
SUCCESSFUL EXPERIENCES WITH Table | 9 |
Copyright | |
50 other sections not shown
Common terms and phrases
algorithm analog analog circuits analysis applied array ASICS ATPG boundary scan burn-in cache cell chip circuitry clock CMOS column Computer cost cycle database debug decoder delay test device diagnosis DUT board failure fault coverage fault free fault model fault simulation fault-free faulty circuit flip-flops frequency functional test fuzzy logic gate gate delay hardware IDDQ testing IEEE IEEE Trans implementation initial input interconnect INTERNATIONAL TEST CONFERENCE IState latches manufacturing measurement memory methodology module node non-robust observability operation output Paper parallel parameters partial scan partition path delay faults performance probe problem Proc procedure processor propagation reset robust scan chain selected sequence sequential shown in Figure signal silicon stuck-at faults substrate Table technique Test Conf test pattern Test SPC test vector testability tester tion tool transistor transition values VLSI voltage wafer