DRAM Circuit Design: Fundamental and High-Speed Topics
John Wiley & Sons, Dec 4, 2007 - Technology & Engineering - 440 pages
A modern, comprehensive introduction to DRAM for students and practicing chip designers
Dynamic Random Access Memory (DRAM) technology has been one of the greatestdriving forces in the advancement of solid-state technology. With its ability to produce high product volumes and low pricing, it forces solid-state memory manufacturers to work aggressively to cut costs while maintaining, if not increasing, their market share. As a result, the state of the art continues to advance owing to the tremendous pressure to get more memory chips from each silicon wafer, primarily through process scaling and clever design.
From a team of engineers working in memory circuit design, DRAM Circuit Design gives students and practicing chip designers an easy-to-follow, yet thorough, introductory treatment of the subject. Focusing on the chip designer rather than the end user, this volume offers expanded, up-to-date coverage of DRAM circuit design by presenting both standard and high-speed implementations. Additionally, it explores a range of topics: the DRAM array, peripheral circuitry, global circuitry and considerations, voltage converters, synchronization in DRAMs, data path design, and power delivery. Additionally, this up-to-date and comprehensive book features topics in high-speed design and architecture and the ever-increasing speed requirements of memory circuits.
The only book that covers the breadth and scope of the subject under one cover, DRAM Circuit Design is an invaluable introduction for students in courses on memory circuit design or advanced digital courses in VLSI or CMOS circuit design. It also serves as an essential, one-stop resource for academics, researchers, and practicing engineers.
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The DRAM Array
The Peripheral Circuitry
Global Circuitry and Considerations
An Introduction to HighSpeed DRAM
HighSpeed Die Architectures
Input Circuit Paths
Output Circuit Paths
32-Mbit block alignment array core bitline C/A CLK capacitance capacitor capture latches CAS latency cell clock cycles clock divider clock domain clock frequency clock signal clock tree CMOS column address column cycle column decoder column select command clock command decoder data path data rate DDR SDRAM delay line delay stages delay-locked loop demultiplexer device diagram digitline architecture digitline pairs domino logic DRAM array DRAM designs FIFO folded digitline gate GDDR3 GDDR4 high-performance DRAM high-speed I/O lines IEEE Journal implementation input buffer inverter jitter Journal of Solid-State layout lock loop match mbit memory array muxes NMOS open digitline operation performance peripheral array logic peripheral logic interface phase detector PRECHARGE predecode RdCLK redundant row address Row decode SDRAM sense amplifier shown in Figure signal Solid-State Circuits Symposium on VLSI synchronous transistors VCDL VLSI Circuits WDQS wordline wordline driver Write data Write latency