Proceedings of the ... ACM Great Lakes Symposium on VLSI.ACM Press, 2005 - Integrated circuits |
Contents
Low Power Test Generation for Path Delay Faults using Stability Functions | 8 |
Interconnect Delay Minimization through Interlayer Via Placement in 3D ICs | 20 |
S2 4S Accounting for the Skin Effect during Repeater Insertion | 32 |
Copyright | |
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algorithm analog circuit and/or a fee application approach architecture asynchronous ATPG bear this notice benchmark bits block buffer cache cache coherence capacitance cell chip circuit clock CMOS Computer Computer-Aided Design configuration constraints Copyright 2005 ACM crosstalk current mirror cycle delay device digital or hard domino domino logic dynamic Elmore delay energy evaluation fault flip-flop FPGA frequency function gate global hardware IEEE implementation increase input instruction Integrated Circuits interconnect latch layout load logic memory method modules MOSFET node noise on-chip operation optimization output parameters path performance phase pipeline placement PLBs post on servers power dissipation POWER4 prior specific permission problem Proc processor proposed redistribute to lists reduce routing scheme Section shown in Figure signal simulation skew specific permission and/or SRAM substrate subthreshold leakage switching Table technique transistor transition variables vector VLIW VLSI voltage width wire Xilinx