Fifth Annual IEEE International Conference on Wafer Scale Integration: 1993 Proceedings : [ICWSI '93] : San Francisco, California, USA |
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Contents
WSI Devices | 1 |
MemoryBased Reasoning Implemented by Wafer Scale Integration | 11 |
The Development of the WASP 3 Processor | 20 |
Copyright | |
27 other sections not shown
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Common terms and phrases
achieved additional algorithm allows applications approach architecture array assembly associated basic block bond buffer cell chip circuit clock columns communication complexity components Computer configuration connections considered contains cost coverage defect delay developed devices direction distribution driver effect elements error example fail-safe failure fault tolerance Figure frequency function given hybrid-WSI IEEE implementation improvement increase input interconnection laser layer logic memory module multiplier node operation optimization output packaging parallel path performance pixel possible presented problem processor programming propagation reconfiguration reduced redundancy referred reliability resistance routing Scale Integration shown shows signal silicon simulation single speed stack step structure substrate switch Table techniques thermal tree unit values vectors VLSI Wafer Scale WASP yield
Bibliographic information
| Title | Fifth Annual IEEE International Conference on Wafer Scale Integration: 1993 Proceedings : [ICWSI '93] : San Francisco, California, USA |
| Author | International Conference on Wafer Scale Integration |
| Editors | Peter W. Wyatt, R. Mike Lea |
| Contributors | IEEE Computer Society, IEEE Components, Hybrids, and Manufacturing Technology Society |
| Publisher | IEEE Computer Soc. Press, 1993 |
| Original from | the University of California |
| Digitized | Jul 27, 2007 |
| ISBN | 0780308670, 9780780308671 |
| Length | 374 pages |
| Export Citation | BiBTeX EndNote RefMan |