Proceedings: May 15-18, 2002, Boston, Massachusetts, USA.. 32 (2002)Inst. of Electrical and Electronics Engineers, 2002 |
Contents
Logical Design | 2 |
Algebra I | 8 |
Partial Hyperclones on a Finite Set | 17 |
Copyright | |
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Common terms and phrases
&-formula adders algorithm application arithmetic axioms of Boolean binary bisemilattice bits block Boolean algebra Boolean functions CMOS coefficients complete components computation corresponding cubes decision diagrams defined denote digit DSMs element Encoded equation ESOP example expressions fault Figure finite full adder function f gate graph IEEE implementation input interlaced bilattice lattice Lemma linear logic circuits logic functions logic value matrix method minterm MLDRAM monoid multi-valued multi-valued logic multiple multiple-valued functions Multiple-Valued Logic MV-algebras MVL circuit MVSIS number of nodes obtained operation output p-valued partial hyperclone partial hyperoperation polarity Proc Proof quantum Reed-Muller Reed-Muller expansions representation represented Schmitt circuits set of axioms shown shows Sierpinski gasket signal simulation subset technique ternary ternary logic Theorem threshold function tion transform transistor truth table truth value unary operation Valued Logic variable vector VLSI voltage X₁