## Multiple-valued Logic: Proceedings |

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### Contents

A Functional Characterization of Post Algebras | 8 |

A Fuzzy Logic Chip and a Fuzzy Inference Accelerator for RealTime Approximate | 25 |

Nonassociativc Boolean Rings | 40 |

Copyright | |

19 other sections not shown

### Common terms and phrases

3-valued algebraic lattice algorithm Boolean rings chip clone CMOS complete lattice Computer corresponding cover CP-gate cube cubical array current mirror current-mode decoder defined Definition denote disjoint ECSA theory elements encoder equation Espresso-MV example expert system FESIP Figure finite flip-flops full adder function f fuzzy logic gate array given half adder Hence IEEE Trans implemented input irredundant isomorphic lattice Lemma linear logic circuits logic value matrix maximal sets minimization minterms mixed-valued multiple-valued logic multiplication multivalued logic obtained operation orthogonal functions output P-ternary paper pass transistors path pattern matching prime implicants Proc product term Proof quaternary realized regular ternary logic representation satisfies shown in Fig signals simulation subset switch Table ternary logic function ternary signal Theorem three-valued threshold detector threshold voltage tion transistors tri-flop unary valued logic variables vector VLSI