Proceedings: The Seventeenth International Symposium on Multiple-Valued Logic, May 26-28, 1987, Boston, Massachusetts, USA |
Contents
A Functional Characterization of Post Algebras | 8 |
A Fuzzy Logic Chip and a Fuzzy Inference Accelerator for RealTime Approximate | 25 |
Nonassociative Boolean Rings | 40 |
Copyright | |
19 other sections not shown
Common terms and phrases
3-valued algorithm Boolean rings chip clone CMOS complete lattice Computer cover CP-gate cube cubical array current-mode decoder defined Definition denote disjoint distributive lattice elements encoder equation Espresso-MV example FESIP Figure finite finite fields flip-flops formula full adder function f fuzzy logic gate given HALF ADDER hedge algebra Hence IEEE Trans implementation input irredundant isomorphic lattice Lemma linear logic circuits logic value matrix maximal minimization minterms mixed-valued multiple-valued logic multiplication nonassociative Boolean ring obtained operation orthogonal functions output P-ternary paper pass transistors path permutation group Post algebras pps functions prime implicants Proc product term Proof quaternary realized representation result satisfies subset switch T₁ Table ternary logic functions ternary signal Theorem three-valued tion transistors tri-flop truth table unary valued logic variables vector VLSI voltage