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14 LINCON runs arithmetic logic unit average latency clock cycles coincident error combinatorial logic comparison monitoring system coverage factors detected by MATMUL detected faults distinguishable faults eight program iterations estimate evaluate failed to produce fault coverage fault simulator fault-tolerant digital computer fault-tolerant system faults detected faults that failed floating-point Gate Logic System gate-level GGLOSS simulation good-machine signature GOTO LABEL implementation Injected faults input iteration of LINCON L1.ELSE laboratory prototype Langley Research Center latent faults LINCON program Logic System Simulator loop LOOP1 majority of faults McGough microcode microprocessor design microsequencer MISR NASA netlist nonanswer number of faults percent produce an answer program iteration proportion proportion of distinguishable proportion of faults prototype hardware pseudorandom R_EXIT_1 RESULT,TEMPX Run2 Rung Runi Runi2 S-GGLOSS study self-test simulated faults simulation results simulation strategy Simulator GGLOSS stuck-at faults SUBROUTINE Swern Table TEMPK TEMPM TEMPM,1 TEMPM,MARRAY,TEMPK RETURN TEMPX tion undetected unfaulted voting frame