Computer ArchitectureThe representation of information; Gates and elementary logic; Storage mechanisms; Putting the bits together; An elementary machine; Variation in addressing; Variations in input/output; Other instructions; The micro computer; Very large computers; Parallelism and distributed logic; Tessellated computers. |
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Page 21
... four bits to store the 5 and an- other four bits to store the 6. Thus , 56-0101 0110 ) . It is only one of several possible " weighted " codes where each of the four positions is given a weight and the digit being represented can be ...
... four bits to store the 5 and an- other four bits to store the 6. Thus , 56-0101 0110 ) . It is only one of several possible " weighted " codes where each of the four positions is given a weight and the digit being represented can be ...
Page 29
... four inputs may be either ZERO or ONE , and that the output may also assume either of these values . There are two possible states for input a and two for b . Considering only these two inputs for a moment , there are four possible ...
... four inputs may be either ZERO or ONE , and that the output may also assume either of these values . There are two possible states for input a and two for b . Considering only these two inputs for a moment , there are four possible ...
Page 151
... four addresses together with the op - code had to be specified by the programmer in every instruction . These were quite naturally called four - address computers . For example , an instruction might look like ADD , A , B , C , D and ...
... four addresses together with the op - code had to be specified by the programmer in every instruction . These were quite naturally called four - address computers . For example , an instruction might look like ADD , A , B , C , D and ...
Contents
THE REPRESENTATION OF INFORMATION | 1 |
GATES AND ELEMENTARY LOGIC | 29 |
STORAGE MECHANISMS | 51 |
Copyright | |
17 other sections not shown
Common terms and phrases
accumulator active adder Address Register addressed memory algorithm arithmetic array binary block bubble byte CACS-I called cell circuit clock clockwise co-ordinate addressed comparand register content addressable copy core cryotrons data bus decoding digits distributed logic drive strap drum execute FETCH flip-flop four full adder gate Goodyear Aerospace I/O device index registers input instruction register interrupt jump load loop machine magnetic main store mask Memory Address Register Memory Buffer Register micro Microprogramming minor cycle op-code operand operation output parallel parametron path position processor program counter pulse pushdown stack Question queue register group reset responders response store S₁ scratch pad shift register shown in Fig signal Signetics 2650 skip specify speed Staran storage Strobe subroutine Suppose tag bit tion transfer TWO's complement vector voltage wire word write ZERO ZERO's