Computer ArchitectureThe representation of information; Gates and elementary logic; Storage mechanisms; Putting the bits together; An elementary machine; Variation in addressing; Variations in input/output; Other instructions; The micro computer; Very large computers; Parallelism and distributed logic; Tessellated computers. |
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Page 29
... inputs may be either ZERO or ONE , and that the output may also assume either of these values . There are two possible states for input a and two for b . Considering only these two inputs for a moment , there are four possible ...
... inputs may be either ZERO or ONE , and that the output may also assume either of these values . There are two possible states for input a and two for b . Considering only these two inputs for a moment , there are four possible ...
Page 31
... inputs . With 4 inputs there are 16 possible input combinations . For each of these input combinations we can choose one of two possible outputs . There are , therefore , 2x2x ... 16 times , or 216 possible black boxes with 4 inputs ...
... inputs . With 4 inputs there are 16 possible input combinations . For each of these input combinations we can choose one of two possible outputs . There are , therefore , 2x2x ... 16 times , or 216 possible black boxes with 4 inputs ...
Page 35
... inputs of an OR element ( one to each input ) . This OR must have as many inputs as there are ONE's in the output column of the truth table . Our job is done . For any input combination that should produce an output of ONE , we have ...
... inputs of an OR element ( one to each input ) . This OR must have as many inputs as there are ONE's in the output column of the truth table . Our job is done . For any input combination that should produce an output of ONE , we have ...
Contents
THE REPRESENTATION OF INFORMATION | 1 |
GATES AND ELEMENTARY LOGIC | 29 |
STORAGE MECHANISMS | 51 |
Copyright | |
17 other sections not shown
Common terms and phrases
accumulator active adder Address Register addressed memory algorithm arithmetic array binary block bubble byte CACS-I called cell circuit clock clockwise co-ordinate addressed comparand register content addressable copy core cryotrons data bus decoding digits distributed logic drive strap drum execute FETCH flip-flop four full adder gate Goodyear Aerospace I/O device index registers input instruction register interrupt jump load loop machine magnetic main store mask Memory Address Register Memory Buffer Register micro Microprogramming minor cycle op-code operand operation output parallel parametron path position processor program counter pulse pushdown stack Question queue register group reset responders response store S₁ scratch pad shift register shown in Fig signal Signetics 2650 skip specify speed Staran storage Strobe subroutine Suppose tag bit tion transfer TWO's complement vector voltage wire word write ZERO ZERO's