VHDL Designer’s Referencetoo vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to logical simulation or synthesis. To the very beginner, VHDL appears as a "kit". He is quickly aware that his problem may be solved with VHDL, but does not know how. He does not even know how to start. In this state of mind, all the constraints that can be set to his modeling job, by using a subset of the language or a given design methodology, may be seen as a life preserver. The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: • Why choose VHDL? • Which VHDL tools should be chosen? • Which modeling methodology should be adopted? • How should the VHDL environment be customized? • What are the tricks? Where are the traps? • What are the differences between VHDL and other competing HDLs? Answers to these questions are organized according to different concerns: buying the tools, organizing the environment, and designing. Decisions taken in each of these areas may have many consequences on the way to the acceptance and efficiently use of VHDL in a company. |
Contents
VHDL TOOLS | 21 |
1 Waiting Procedure | 34 |
Introduction | 44 |
VHDL AND MODELING ISSUES | 45 |
2 Semantics of VHDL Half Adder | 47 |
12 Unresolved Aggregate Signal | 60 |
19 VHDL Libraries | 73 |
21 Synthesis View of Entity ADD | 88 |
System Modeling | 145 |
STRUCTURING METHODOLOGY | 147 |
Structuring Methodology | 161 |
TRICKS AND TRAPS | 165 |
Tricks and Traps | 169 |
and VHDL | 205 |
VERILOG AND VHDL | 231 |
Verilog and VHDL | 267 |
VHDL Tools 3 VHDL and Modeling Issues | 98 |
STRUCTURING THE ENVIRONMENT | 99 |
2 Modeling Tristate Buses | 104 |
6 Datapath Operators | 126 |
SYSTEM MODELING | 129 |
UDLI AND VHDL | 319 |
1 | 325 |
8a Automaton | 383 |
Memo 12 Index | 392 |
Other editions - View all
VHDL Designer’s Reference Jean-Michel Bergé,Alain Fonkoua,Serge Maginot,Jacques Rouillard Limited preview - 1992 |
VHDL Designer’s Reference Jean-Michel Bergé,Alain Fonkoua,Serge Maginot,Jacques Rouillard No preview available - 2012 |
Common terms and phrases
A'LENGTH architecture array associated behavior bit arrays block statement clause CLOCK compiled concurrent statements configuration continuous assignment conversion function corresponding dataflow datatypes debugging defined delay design entity design units downto driver driving value effective value end block end component end loop end process entity declaration enumeration type equivalent example executed expression formal verification gate guarded signals hardware description language implementation inout input instantiation INTEGER integrated circuits LATCH logic synthesis logic system logic type logic values module multi-value logic nand netlist output package body package declaration parameter port map predefined procedural assignment process begin process statement recompilation reference manual resolution function RESULT return BIT_VECTOR semantics signal assignment statement specification STD_LOGIC_VECTOR STD_ULOGIC subelements subprograms subtype synthesis tools translation type BIT type conversion UDL/I UDLI_BIT user-defined vector Verilog VHDL model VHDL process VHDL text VHDL tools wait statement waveform XBIT