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32nd Design Automation algorithm applied approach ASIC assignment behavior benchmark block Boolean bound buffer capacitance CDFG cell clock period CMOS complexity components computation Computer-Aided Design constraints corresponding cost cube cycle decomposition defined delay denote Design Automation Conference edge efficient Elmore delay equation equivalent example execution fanout fault coverage fault simulation fee and/or specific Figure FPGA function gate graph hardware heuristic high level synthesis IEEE implementation input integration interconnect interface iteration layout linear logic logic synthesis mapping method methodology minimize module netlist node OBDD opamp operations optimization output partitioning path performance phase placement problem Proc procedure retiming routing schedule Section sequence sequential circuits shown signal skew solution switching synchronous synthesis Table techniques tion tool topology transformation transistor tree variables vector verification Verilog vertex VHDL VLSI voltage wire