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WSI Development Programs
Circuits and Technology1
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achieve active algorithm allows analysis applications approach architecture array associated block building channel chip circuit clock column communication compared complete Computer configuration connected cost defects described developed device distribution effects elements example expected fabrication failure fault fault tolerance faulty cell Figure four functional given IEEE implementation improvement increase initial input Integration interconnection internal laser layout limited linear logic mapping memory metal modules multiple needed node operation parallel paths pattern performed possible present problem processor production proposed reconfiguration redundancy repair represent routing scheme selected shown in Figure shows signal simulation single spare step structure switches systolic Table technique tracks tree vertical VLSI voltage Wafer Scale wire yield