Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute
This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes System Verilog and Verilog-AMS.
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Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic ...
John Michael Williams
No preview available - 2016
AdjustFreq always@(posedge assertion back-annotation begin bits bitwise operators blocking assignments boundary scan byte chip clock domains ClockIn combinational logic compilation component concurrent connect copy correctly count counter declared decoder default DesDecoder Deserializer edge endmodule error event control example expression FIFO flip-flop frequency FullDup functionality gate hardware hierarchy IEEE Std implemented initial block input instance instantiation integer Intro_Top JTAG Lab Postmortem latch loop memory module header module named NextState nonblocking assignments operators optional output port Palnitkar parameter parity PCI Express posedge race conditions rename Reset scan chain schematic SDF file sequential sequential logic SerDes serial clock serial data shift register shown in figure specify block specparam Step subdirectory switch-level synchronization synthesized netlist SystemVerilog task testbench Thomas and Moorby trireg TSMC variable vector verilog VLSI width wire