The SIMD Model of Parallel Computation
Springer Science & Business Media, Dec 6, 2012 - Computers - 149 pages
1.1 Background There are many paradigmatic statements in the literature claiming that this is the decade of parallel computation. A great deal of research is being de voted to developing architectures and algorithms for parallel machines with thousands, or even millions, of processors. Such massively parallel computers have been made feasible by advances in VLSI (very large scale integration) technology. In fact, a number of computers having over one thousand pro cessors are commercially available. Furthermore, it is reasonable to expect that as VLSI technology continues to improve, massively parallel computers will become increasingly affordable and common. However, despite the significant progress made in the field, many funda mental issues still remain unresolved. One of the most significant of these is the issue of a general purpose parallel architecture. There is currently a huge variety of parallel architectures that are either being built or proposed. The problem is whether a single parallel computer can perform efficiently on all computing applications.
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active records algorithm requires architecture array locations assigned band_totals binary bit position bit-serial bitonic merge bitonic sort buckets calculated chip CLIP4 clock column consists constant of proportionality data items data-dependent descend algorithms distributed memory efficiently fetch-and-add full adder global Gray code Hough transform hypercube-derived computer image processing implemented input interconnection network intermediate destinations labeling large number loaded logical processor lookup memory computers mesh connected computer MIMD monotonic permutation Nassimi neighbors node number of processors output pairs Parallel Algorithms parallel computers perform phase pixels plain hypercube computer plain mesh connected pointer PRAM processor-based processors puter pyramid computer random RAR algorithms RAR operations RAW and RAR result rithms router row-major row-major ordering scan operation Section segmented scan shared memory locations shifted significant bit SIMD simulation single solved sorted lists stages stored switches synchronous technique tion topology tree computer x x x