International Conference on Simulation and Hardware Description Languages (ICSHDL): Proceedings of the 1994 Western MultiConference, January 24-26, 1994, Radisson Tempe Mission Palms, Tempe, ArizonaPhilip A. Wilsey, David Rhodes |
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Page 174
... circuit extractor provides the circuit parameters and circuit geometry for the entire layout based on the electrical properties of the constituent material polygons which form nodes and transistors in the layout [ SO85 ] . From this ...
... circuit extractor provides the circuit parameters and circuit geometry for the entire layout based on the electrical properties of the constituent material polygons which form nodes and transistors in the layout [ SO85 ] . From this ...
Page 179
... circuit design environment and to improve the design / verification turn - around time [ OHM + 85 ] ! " Magic's circuit database is made up of some number of cells , each of which contains rectangles representing a sub - circuit . These ...
... circuit design environment and to improve the design / verification turn - around time [ OHM + 85 ] ! " Magic's circuit database is made up of some number of cells , each of which contains rectangles representing a sub - circuit . These ...
Page 180
... circuit layout . This reduces the amount of information processed by the simulator and lets the designer focus on that part of the circuit layout of interest . INTERSPICE allows the designer to select any sub- circuit in the layout ...
... circuit layout . This reduces the amount of information processed by the simulator and lets the designer focus on that part of the circuit layout of interest . INTERSPICE allows the designer to select any sub- circuit in the layout ...
Contents
Functional Specification and Simulation | 3 |
Cohn | 9 |
Simulator Characteristics Needed to Interface | 31 |
Copyright | |
12 other sections not shown
Common terms and phrases
abstract AHDL alen algorithm analog analog circuit analysis architecture behavior binary block Boolean cell circuit clock command compiler complexity component Computer Conference on Simulation decoder defined delay delay calculation described Description Languages ICSHDL Discrete Event Simulation driver entity event pattern example execution fault simulation FIFO formal verification full adder gate level goto Hardware Description Languages hierarchical ICM2 IEEE implementation input int_in integer Intel iPSC/2 interface Intermetrics INTERSPICE ISIG layout logic loop MHDL minterm mode module netlist node operations output parameters partition port PROTO queue represented rollback relaxation scheduling semantics sequence sequential Simulation and Hardware simulation cycle specification SPICE standard structure sub-circuit switch level synthesis tion TLVHDL transistor transition transputers variable vector verify Verilog VHDL description VHDL model VHDL processes VHDL simulation VLSI voltage Wilsey and Rhodes