International Conference on Simulation and Hardware Description Languages (ICSHDL): Proceedings of the 1994 Western MultiConference, January 24-26, 1994, Radisson Tempe Mission Palms, Tempe, ArizonaPhilip A. Wilsey, David Rhodes |
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Page 181
... layout for timing analysis : Gate - level delay determination via Silicon Compilation Eraj Basnayake and J. W. Smith Computer Science Department , University of Georgia Proceedings of the International Conference on Simulation and ...
... layout for timing analysis : Gate - level delay determination via Silicon Compilation Eraj Basnayake and J. W. Smith Computer Science Department , University of Georgia Proceedings of the International Conference on Simulation and ...
Page 184
... layout . 3.2.2 Standard Cell Routing A router needs information regarding the position of the cells in a layout , pin names , and a netlist specifying the interconnec- tions . For instance , the VerSiCo system used Magic's router ...
... layout . 3.2.2 Standard Cell Routing A router needs information regarding the position of the cells in a layout , pin names , and a netlist specifying the interconnec- tions . For instance , the VerSiCo system used Magic's router ...
Page 185
... layout , and place reality - based timing values back into the original HDL description , transparently to the user . The VLSI layout can be used as a fast prototype of the circuit described . The generated layout is an accurate mapping ...
... layout , and place reality - based timing values back into the original HDL description , transparently to the user . The VLSI layout can be used as a fast prototype of the circuit described . The generated layout is an accurate mapping ...
Contents
Functional Specification and Simulation | 3 |
Cohn | 9 |
Simulator Characteristics Needed to Interface | 31 |
Copyright | |
12 other sections not shown
Common terms and phrases
abstract AHDL alen algorithm analog analog circuit analysis architecture behavior binary block Boolean cell circuit clock command compiler complexity component Computer Conference on Simulation decoder defined delay delay calculation described Description Languages ICSHDL Discrete Event Simulation driver entity event pattern example execution fault simulation FIFO formal verification full adder gate level goto Hardware Description Languages hierarchical ICM2 IEEE implementation input int_in integer Intel iPSC/2 interface Intermetrics INTERSPICE ISIG layout logic loop MHDL minterm mode module netlist node operations output parameters partition port PROTO queue represented rollback relaxation scheduling semantics sequence sequential Simulation and Hardware simulation cycle specification SPICE standard structure sub-circuit switch level synthesis tion TLVHDL transistor transition transputers variable vector verify Verilog VHDL description VHDL model VHDL processes VHDL simulation VLSI voltage Wilsey and Rhodes