IEICE Transactions on ElectronicsInstitute of Electronics, Information and Communication Engineers, 2008 - Electronics |
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A/D converter algorithm Appl applications architecture bandwidth bias block cache calculated capacitance capacitor cell chip clock CMOS Communication Engineers configuration conventional core cryocooled devices electrical fabricated Figure filter FPGA frequency function gate Gbps IEEE IEEE Trans IEICE input Institute of Electronics instruction integrated integrated circuits interconnect Japan Josephson Josephson junctions layer leakage logic Manuscript measured memory metamaterials mode modulator MOSFET NEC Corporation node noise on-chip operation optical optical flow output paper parameters performance phase Photonics pixel power consumption processor proposed received the B.S. reduce resonator RSFQ sampling scattering search range semiconductor SFQ circuits shown in Fig shows signal silicon simulation Special Section SRAM structure Supercond superconducting switch Tech technique temperature tion Tokyo transistors transmission University University of Tokyo VLSI voltage wave waveguide width