Structured Computer OrganizationCompletely updated, this book explains how computer designers can follow the structured model to develop efficient hardware and software systems. New information has been included on UNIX, OS/2, INTEL 8088/80286/80386, Motorola 68000/68020/68030 and RISC machine. The operation of a typical IBM PC clone is now described in detail at the chip level. |
From inside the book
Results 1-3 of 95
Page 114
Andrew S. Tanenbaum. Addressing Bus arbitration Data Coprocessor Bus control Typical Micro- Processor Status Interrupts Miscellaneous Symbol for clock signal 11 Φ +5 ↑ Symbol ... bus Buses ALU Local bus 114 CHAP . 3 THE DIGITAL LOGIC LEVEL.
Andrew S. Tanenbaum. Addressing Bus arbitration Data Coprocessor Bus control Typical Micro- Processor Status Interrupts Miscellaneous Symbol for clock signal 11 Φ +5 ↑ Symbol ... bus Buses ALU Local bus 114 CHAP . 3 THE DIGITAL LOGIC LEVEL.
Page 115
Andrew S. Tanenbaum. CPU Registers On - chip bus Buses ALU Local bus Coprocessor System bus Memory board 1/0 board 1/0 board Fig . 3-32 . Computer systems can have multiple buses . A number of buses are in widespread use in the computer ...
Andrew S. Tanenbaum. CPU Registers On - chip bus Buses ALU Local bus Coprocessor System bus Memory board 1/0 board 1/0 board Fig . 3-32 . Computer systems can have multiple buses . A number of buses are in widespread use in the computer ...
Page 163
... Buses A bus is a collection of wires used to transmit signals in parallel . For example , buses are used to allow the contents of one register to be copied to another one . Unlike the system buses we studied in Chap . 3 , these buses ...
... Buses A bus is a collection of wires used to transmit signals in parallel . For example , buses are used to allow the contents of one register to be copied to another one . Unlike the system buses we studied in Chap . 3 , these buses ...
Other editions - View all
Common terms and phrases
address space addressing modes algorithm architecture arithmetic assembly language asserted binary bits block Boolean buffer bus cycle buses bytes cache chip circuit CISC clock compiler contains control store coprocessor data path decoding descriptor digits direct addressing disk entry example executed fetch field floating-point function gates goto hardware I/O devices IEEE implement input instruction set integer Intel interrupt jump latch loaded loop machine language macro main memory memory address memory word microinstruction microprocessor microprogram MIPS Motorola MULTICS multiple multiprocessor needed nsec object module opcode operand operating system output parallel parameters performance pins problem procedure call processor program counter result RISC RISC machines segment registers semaphore sequence shown in Fig signal SPARC specified switch symbol tion UNIX variables vector virtual address virtual memory Virtual page write