Structured Computer OrganizationCompletely updated, this book explains how computer designers can follow the structured model to develop efficient hardware and software systems. New information has been included on UNIX, OS/2, INTEL 8088/80286/80386, Motorola 68000/68020/68030 and RISC machine. The operation of a typical IBM PC clone is now described in detail at the chip level. |
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Page 38
... processors , each one using its own data from its own memory ( loaded during the initialization phase ) . The array processor is especially well - suited to calcula- tions on matrices . Flynn's third category is MIMD , in which ...
... processors , each one using its own data from its own memory ( loaded during the initialization phase ) . The array processor is especially well - suited to calcula- tions on matrices . Flynn's third category is MIMD , in which ...
Page 124
... Processor A reads word x and sees that it is zero ( bus cycle 0 ) . 2. Processor B reads word x and sees that it is zero ( bus cycle 1 ) . 3. Processor A writes 1 into word x ( bus cycle 2 ) . 4. Processor B writes 1 into word x ( bus ...
... Processor A reads word x and sees that it is zero ( bus cycle 0 ) . 2. Processor B reads word x and sees that it is zero ( bus cycle 1 ) . 3. Processor A writes 1 into word x ( bus cycle 2 ) . 4. Processor B writes 1 into word x ( bus ...
Page 526
... processor ) with one or more inputs and one or more outputs . Consider the box labeled " 6 " in Fig . 8-56 . It has two inputs and an output . As soon as packets have arrived on each input line and the previously sent output packet has ...
... processor ) with one or more inputs and one or more outputs . Consider the box labeled " 6 " in Fig . 8-56 . It has two inputs and an output . As soon as packets have arrived on each input line and the previously sent output packet has ...
Contents
INTRODUCTION | 1 |
THE OPERATING SYSTEM MACHINE LEVEL | 6 |
THE MICROPROGRAMMING LEVEL | 161 |
Copyright | |
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addition address space allow architecture arithmetic assembly asserted begin binary bits block buses byte cache called carry character chip circuit clock compiler complete condition connected consists contains cycle decoding device disk entry error example executed fetch field Figure four function gates gives hardware implement input instruction Intel interpreter interrupt jump language latch lines loaded logical machine means memory microinstruction microprogram mode move multiple needed opcode operand operating system output parallel performance pins pointer possible present problem procedure processor produce reference request requires result RISC segment shown in Fig shows signal simple single specified stack symbol tion transfer unit variables vector virtual write