Abnormal fault-recovery characteristics of the fault-tolerant multiprocessor uncovered using a new fault-injection methodology
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anomalous behavior bus error latch buses Byzantine faults causing a lying configuration corruption data acquisition system denotes diagram of error-latch equation error detection error occurred error-latch data error-latch processing error-latch read sequence error-latch read transactions error-latch values fault occurs fault-injection experiment Fault-Injection Methodology fault-management software Fault-Tolerant Multiprocessor fault-tolerant systems faulty LRU faulty unit FFE1 FFEO FFEO FFEO FFEO FFEO P1 Figure hard fault holding the bus intermittent faults Langley Research Center last LRU latch of LRU latches are read latches indicating LRU 9 LRU is disabled LRU LRU LRU lying event lying LRU lying-fault syndrome msec NASA number of faults performed polling sequence probability PROC PROC PROC processor triad R T LRU read operation reading the error redundant reported error second LRU sequence of LRU's signals simplex read system bus System crash tion TMR system transactions of LRU triad reading Triple Modular Redundancy Variability of NF