Abnormal Fault-recovery Characteristics of the Fault-tolerant Multiprocessor Uncovered Using a New Fault-injection MethodologyNational Aeronautics and Space Administration, Office of Management, Scientific and Technical Information Division, 1991 - Electronic digital computers - 17 pages |
Contents
Summary | 1 |
Subsystem Interaction Leading to Anomalous Behavior | 8 |
Lying Events on a Triple Modular Redundancy System | 16 |
Common terms and phrases
anomalous behavior bus error latch buses Byzantine faults causing a lying configuration corruption data acquisition system denotes diagram of error-latch equation error detection error occurred error-latch data error-latch processing error-latch read sequence error-latch read transactions error-latch values fault occurs fault-management software Fault-Tolerant Multiprocessor fault-tolerant systems faulty LRU faulty unit FFE1 FFEO FFEO FFEO FFEO FFEO P1 Figure FTMP hard fault holding the bus intermittent faults Langley Research Center last LRU latch of LRU latches are read latches indicating LRU 9 LRU is disabled LRU LRU LRU LRU's disabled lying event lying LRU lying-fault syndrome msec NASA number of faults performed polling sequence probability PROC PROC PROC processor triad read operation reading the error redundant reported error SBC TO READ second LRU sequence of LRU's signals simplex read system bus System crash System memory triad tion TMR system transactions of LRU triad reading Triple Modular Redundancy