Planar Test Structures for Characterizing Impurities in Silicon, Volume 13 |
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automatic data processing base-collector gated diode Bureau of Standards C-V dopant profile Caughey-Thomas 11 Characterizing Impurities closed-form formula collector four-probe resistor collector MOS capacitor Cross sectional view Debye length defect centers density for n-type depletion region depletion width devices difference versus dopant diffused layer dopant density relation dopant profiles taken figure 16 Figure 17 four-probe resistor 3.17 gold acceptor Irvin curve Junction C-V junction for various lifetime and leakage M. G. Buehler MOS capacitor 3.8 MOS capacitor C-V n-type MOS capacitors n-type silicon 300 National Bureau Normalized resistivity difference orthogonal p-n junctions Pauw formula Pauw sheet resistor Pauw structure photomask Planar Test Structures resistivity difference versus resistivity versus dopant Semiconductor Measurement Technology sheet resistance shown in figure silicon 300 K small base-collector gated stimulated current response Structures for Characterizing TEMPERATURE test pattern Thermally stimulated current van der Pauw various heating rates versus dopant density wafer well-designed and miniaturized