Verilog HDL: A Guide to Digital Design and Synthesis, Volume 1VERILOG HDL, Second Editionby Samir PalnitkarWith a Foreword by Prabhu GoelWritten forboth experienced and new users, this book gives you broad coverage of VerilogHDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard. Among its many features, this edition- bull; bull;Describes state-of-the-art verification methodologies bull;Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling bull;Introduces you to the Programming Language Interface (PLI) bull;Describes logic synthesis methodologies bull;Explains timing and delay simulation bull;Discusses user-defined primitives bull;Offers many practical modeling tips Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter. About the CD-ROMThe CD-ROM contains a Verilog simulator with agraphical user interface and the source code for the examples in the book. Whatpeople are saying about Verilog HDL- "Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today'smost complex digital designs. This book is valuable to both the novice and theexperienced Verilog user. I highly recommend it to anyone exploring Verilogbased design." -RajeevMadhavan, Chairman and CEO, Magma Design Automation "Thisbook is unique in its breadth of information on Verilog and Verilog-relatedtopics. It is fully compliant with the IEEE 1364-2001 standard, contains allthe information that you need on the basics, and devotes several chapters toadvanced topics such as verification, PLI, synthesis and modelingtechniques." -MichaelMcNamara, Chair, IEEE 1364-2001 Verilog Standards Organization Thishas been my favorite Verilog book since I picked it up in college. It is theonly book that covers practical Verilog. A must have for beginners andexperts." -BerendOzceri, Design Engineer, Cisco Systems, Inc. "Simple,logical and well-organized material with plenty of illustrations, makes this anideal textbook." -Arun K. Somani, Jerry R. Junkins Chair Professor,Department of Electrical and Computer Engineering, Iowa State University, Ames PRENTICE HALL Professional Technical Reference Upper Saddle River, NJ 07458 www.phptr.com ISBN: 0-13-044911-3 |
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book for beginners in verilog
Contents
Hierarchical Modeling Concepts | 11 |
Basic Concepts | 27 |
Modules and Ports | 49 |
GateLevel Modeling | 63 |
Dataflow Modeling | 89 |
Behavioral Modeling | 119 |
Tasks and Functions | 171 |
Useful Modeling Techniques | 187 |
UserDefined Primitives | 251 |
Programming Language Interface | 273 |
Logic Synthesis | 300 |
Advanced Verification Techniques | 341 |
Appendices | 361 |
B List of PLI Routines | 369 |
List of Keywords System Tasks and Compiler Directives | 385 |
E Verilog Tidbits | 421 |
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Common terms and phrases
allows arguments assign attribute_instance basic begin behavioral block c_in called carry cell chapter char circuit clear clock combinational compiler Conditional connection constructs contains continuous assignment count counter declared default defined definition delay described discussed display edge endmodule event Example executed expression FIFO Figure flow formal full adder function gate gate-level handle Hardware hierarchical identifier implementation initial input instance instantiated integer internal keyword language logic synthesis tool loop memory modeling module monitoring multiplexer nets object operands operators optimized output parameter path port primitive reset Ripple routines sequential shows signal signed simulation specified standard statements stimulus strength string switches system task Table terminal transitions types units variables vector verification Verilog HDL wire write
References to this book
Bibliographic information
| Title | Verilog HDL: A Guide to Digital Design and Synthesis, Volume 1 Electrical Engineering: Digital Design Prentice Hall Title Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar |
| Author | Samir Palnitkar |
| Edition | illustrated |
| Publisher | Prentice Hall Professional, 2003 |
| ISBN | 0130449113, 9780130449115 |
| Length | 450 pages |
| Subjects | › › Technology & Engineering / Electronics / General |
| Export Citation | BiBTeX EndNote RefMan |