Cache and Interconnect Architectures in MultiprocessorsMichel Dubois, S. S. Thakkar Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop. |
Contents
VirtualAddress Caches in Multiprocessors | 15 |
SIMULATION AND PERFORMANCE STUDIES CACHE | 33 |
Performance of Symmetry Multiprocessor System | 53 |
Copyright | |
11 other sections not shown
Other editions - View all
Cache and Interconnect Architectures in Multiprocessors Michel Dubois,Shreekant S. Thakkar Limited preview - 2012 |
Cache and Interconnect Architectures in Multiprocessors Michel Dubois,Shreekant S. Thakkar No preview available - 2011 |
Cache and Interconnect Architectures in Multiprocessors Michel DuBois,Shreekant S Thakkar No preview available - 1990 |
Common terms and phrases
14 15 Invalidations 16 processors access burst algorithm applications array Avg invals behavior broadcast bus utilization buses busy-waiting bytes cache block cache coherence protocols cache consistency cache line cache miss chunk Computer Architecture copy Copyback System crossbar data objects directory schemes dual directory execution global hardware consistency IEEE implementation interconnect invalidation patterns invalidation traffic invals per shared iterations large number Linpack load lock LocusRoute machine main memory Maxflow Michel Dubois microtasks modified MP3D multi multiple multiprocessor system nodes number of invalidations number of processors operating system overhead page table parallel loops parallel programs penalty performance physical address problem size Proc read cycles reference bit remote cache request S-blocks SA-TSP scalable scheduling self-scheduling Sequent Computer Systems shared cache shared data shared memory Shared write fraction shared-memory multiprocessor sharing-list solution speedup subsystem Symmetry Synapse task queue test-and-set trace trace-driven simulation transactions uniprocessor updated valid virtual address write-through