CMOS IC Layout: Concepts, Methodologies, and Tools
This book includes basic methodologies, review of basic electrical rules and how they apply, design rules, IC planning, detailed checklists for design review, specific layout design flows, specialized block design, interconnect design, and also additional information on design limitations due to production requirements.
*Practical, hands-on approach to CMOS layout theory and design
*Offers engineers and technicians the training materials they need to stay current in circuit design technology.
*Covers manufacturing processes and their effect on layout and design decisions
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CHAPTER 3 LAYOUT DESIGN
CHAPTER 4 LAYOUT DESIGN FLOWS
CHAPTER 5 ADVANCED TECHNIQUES FOR SPECIALIZED BUILDINGBLOCK LAYOUT DESIGN
CHAPTER 6 ADVANCED TECHNIQUES FOR BUILDINGBLOCK INTERCONNECT LAYOUT DESIGN
CHAPTER 7 LAYOUT DESIGN TECHNIQUES TO ADDRESS ELECTRICAL CHARACTERISTICS
CHAPTER 8 LAYOUT CONSIDERATIONS DUE TO PROCESS CONSTRAINTS
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active AGBC architecture ASIC ASIC flow automation block buffer capacitance capacitor cell libraries circuit design circuitry Cl N/A clock signal Color version complete concept conductor connected database datapath defined design rules devices drain DRAM electromigration example extraction floorplan full-custom functionality gate array GDSII grid guidelines implemented input interconnect interface inverter latch-up layout design layout extraction layout verification logic gates manufacturing process memory cell Mentor Graphics metal methodologies minimize minimum N-well NAND netlist NMOS transistors node optimized options output overlap path place-and-route tools placed placement PMOS PMOS and NMOS polygons polysilicon power supply printed book figure requirements resistance resistor routers routing channels routing layers schematic shown in Figure silicon simulation space specific standard cell step strap substrate tape-out techniques typically verification tools version of printed vias voltage wafer width wordline