Latency Tolerant ArchitecturesStanford University, 1998 - 266 pages |
Contents
Methodology | 18 |
Adapting to Memory Latency | 73 |
Latency tolerated and bandwidth consumed | 82 |
Copyright | |
4 other sections not shown
Common terms and phrases
address correlation table Architecture associative name table branch prediction buffers and victim cache line cache line index cache miss Cache on L2 Cmp Esp Lin Compress Computer configuration define Esp Lin Sc Espresso excess CPI FFT Unc Wav floating point functional units graph impact of memory implemented increasing indirect branch instruction fetch instruction window L1 Cache latency tolerance Lin Sc Spc Linpacks Lisp load instruction load/store lookahead Lsp Benchmark Figure memory bandwidth memory subsystem microprocessor MIPS miss history miss penalty miss rate MXS simulator operation partial hits physical register ports prediction cache prefetch amount prefetching processor model queue register alias table register file register renaming reorder reservation stations Save Ratio Sc Spc FFT source operands Spc FFT Unc speculative execution Spice stream buffers superscalar processor techniques for tolerating tolerating memory latency Unc Wav Lsp Uncompress updated vector processors victim cache Wav Lsp Benchmark Xlisp