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80C186 Modular Core bit is set Bit Name Reset bits are shown bus cycle bus hold Bus Interface Unit bus master byte or word Chip-Select Unit CLKIN CLKOUT clock compatibility with future Control Register coprocessor crystal data bus device DRAM Figure frequency future intel products HLDA Idle mode index register input instruction is executed Instruction Operands instruction prefetch Intel interrupt acknowledge Interrupt Control Unit interrupt handler interrupt request interrupt source interrupt vector Interrupt Vector Table Kbytes logic zero maskable interrupt Maxcount Compare microprocessor Modular Core family mov dx Opcode open-drain operand operation output Peripheral Control Block Pointer port pin Powerdown mode priority processor Refresh Control Unit Register Function Register Mnemonic Reserved bits Reserved register bits Reset State Function serial port shown with gray signal stack Status register Synchronization Timer Count transfer wait zero to ensure