80C186EB/80C188EB User's Manual |
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80C186 Modular Core addressing modes base address base register bit is set Bit Mnemonic Bit Name bits are shown bus cycle bus hold Bus Interface Unit byte or word CLKOUT Control register data bus device equ xxxxh Execution Unit external Figure future Intel products HALT bus HLDA I/O space Idle mode index register input Instruction Pointer instruction prefetch interrupt acknowledge Interrupt Control Unit Interrupt Request interrupt vector Interrupt Vector Table Kbytes Latch logic zero maskable interrupt Maxcount Compare microprocessor Mnemonic Modular Core family mov dx Non-Maskable Interrupt offset Opcode operand operation output Peripheral Control Block phase Port Pin priority Register Function Register Mnemonic Register Name Reserved bits Reserved register bits reset segment registers serial port shown with gray signal single step stack Status register string instruction Synchronization Timer Count Trap Flag valid wait write zero to ensure