Computer Architecture: A Quantitative ApproachComputer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book, which became a part of Intel's 2012 recommended reading list for developers, covers the revolution of mobile computing. It also highlights the two most important factors in architecture today: parallelism and memory hierarchy. This fully updated edition is comprised of six chapters that follow a consistent framework: explanation of the ideas in each chapter; a crosscutting issues section, which presents how the concepts covered in one chapter connect with those given in other chapters; a putting it all together section that links these concepts by discussing how they are applied in real machine; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects. Formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability are included. The book also covers virtual machines, SRAM and DRAM technologies, and new material on Flash memory. Other topics include the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, vector architectures, multicore processors, and warehouse-scale computers (WSCs). There are updated case studies and completely new exercises. Additional reference appendices are available online. This book will be a valuable reference for computer architects, programmers, application developers, compiler and system software developers, computer system designers and application developers. - Part of Intel's 2012 Recommended Reading List for Developers - Updated to cover the mobile computing revolution - Emphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms. - Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next") - Includes three review appendices in the printed text. Additional reference appendices are available online. - Includes updated Case Studies and completely new exercises. |
Contents
| 1 | |
2 Memory Hierarchy Design | 71 |
3 InstructionLevel Parallelism and Its Exploitation | 147 |
4 DataLevel Parallelism in Vector SIMD and GPU Architectures | 261 |
5 ThreadLevel Parallelism | 343 |
6 WarehouseScale Computers to Exploit RequestLevel and DataLevel Parallelism | 431 |
Appendix A Instruction Set Principles | A-1 |
Appendix B Review of Memory Hierarchy | B-1 |
Basic and Intermediate Concepts | C-1 |
| 1 | |
| 1-1 | |
Translation between GPU terms in book and official NVIDIA and OpenCL terms | 1-90 |
Other editions - View all
Computer Architecture: A Quantitative Approach John L. Hennessy,David A. Patterson,Krste Asanović Limited preview - 2012 |
Common terms and phrases
ADD.D addressing modes Appendix Assume average memory access bandwidth benchmarks bits branch branch prediction buffer bytes cache block cache miss Chapter chip clock cycles clock rate coherence compiler Core i7 cost CUDA data cache dependences disk DRAM dynamic scheduling example execution fetch Figure floating-point functional units hardware hazards implementation increase instruction set instruction set architecture integer Intel issue L2 cache latency load loop main memory MapReduce memory hierarchy MIPS miss penalty miss rate multicore multiple multiprocessor multithreading node operands operating system Opteron optimizations parallelism performance pipeline Power7 prediction predictor prefetch protocol reduce Regs requires reservation stations result RISC Section sequence servers set associative shared shows SIMD SIMD instructions SIMD Lanes SIMD Processor SIMD thread speculation speedup stall superscalar thread-level parallelism tion vector processor virtual memory workload write-back