High Speed Computation: Vector ProcessingThe University., 1980 - Vector analysis |
Contents
Depositing into available fields | 2 |
Introduction to Vector Algorithm Organization | 3 |
Device address register opcodes to modify 813 | 8 |
Copyright | |
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Common terms and phrases
ADD XINC algorithm APSTATUS APTR array processor assembly language atom bit-reverse bits BPTI BPTR branch buses calculation clock CYBER data pad bus data structure data transfer data word device address dihedral angles DPBS ECEPP elements energy execution exponent FADD FADDR fetch field Figure FLOATING POINT FLOATING POINT SYSTEMS floating-point floating-point adder floating-point number FMULR format FORTRAN functional units hardware host computer host CPU I/O device INCDPA INCMA inner loop input register instruction cycle instruction word integer interrupt IODRDY loaded main data memory mantissa matrix memory address register MFLOPS mode op-code operands output parallel performance pipeline problem program source memory reset result s-pad s-pad operation scalar SETMA SP SPD sparse sparse matrix SPFN storage stored subroutine supervisor table memory TMRAM vector length vector processor zero