IAPX 86/88, 186/188 User's Manual Hardware Reference |
Common terms and phrases
active ADDRESS BUS address/data ARDY buffer bus arbiter bus cycle bus master byte or word Bytes Coding Example channel program chip select clock cycles Clocks Bytes Coding command configuration control register coprocessor CPU clock CPU's data bus decode delay destination DISP-HI DMA request DMA transfer DT/R enable Encoding execution external fetch Figure Flags FLOAT HLDA I/O device I/O space iAPX immediate inactive input Instruction Set INTA Intel interface internal interrupt acknowledge interrupt controller interrupt request interrupt vector Jump LOCK Logical maximum mode mem8 microprocessor MOD REG R/M MULTIBUS multiplexed ODITSZAPC offset if AA-01 opcode Operands Clocks Transfers operation output peripheral pointer priority processor Programmable Interrupt Controller pulse ready reset short-label signal slave stack status lines synchronized system bus T₁ Table task block timer tion transceivers valid wait write