VLSI Risc Architecture and Organization
With the expectation that architectural improvements will play a significant role inadvancing processor performance, it is critical for readers to maintain an up-to-date, unified overview of technological advances in this vital research area.Gathering into one place material that had been scattered throughout the literaturemakingit difficult to obtain detailed information on computer designs-this importantbook describes the main architectural and organizational features of modem mini- andmicrocomputers. In addition, it explains the RISC philosophy by supplying historicalbackground information and excellent examples of several commercially available RISCmicroprocessors.Limiting attention to VLSI implementations of RISC processors, VLSI RISCArchitecture and Organization offers insight into design issues that arose indeveloping a RISC system, using the VLSI RISC chip set developed at AcornComputers Limited as an example ... discusses options considered during the designprocess, the basis for the decisions made, and implementation details . . . describescontemporary RISC architecture, comparing and contrasting different designs ... andlooks at future trends in RISC research.Discussing the topic cohesively and comprehensively-from initial study into reducedinstructions sets to the widespread introduction of RISC architectures into mainstreamcomputer products-VLSI RISC Architecture and Organization is aninvaluable reference for electrical, electronics, and computer engineers; computerarchitects and scientists; hardware systems designers; and upper-level undergraduate andgraduate students in computer science and electrical engineering courses
What people are saying - Write a review
We haven't found any reviews in the usual places.
32 bits address translation algorithm allow alu+ arithmetic ARM instructions ARM3 bandwidth Berkeley RISC block byte chip CISC compiler condition codes control logic control registers coprocessor coprocessor instructions cycle data operation data transfer datapath destination register DRAM entry execution unit field floating-point function units general-purpose halfword hardware Harvard architecture implementation incremented instruction and data instruction cache instruction decoder instruction formats instruction pipeline instruction prefetch instruction set integer interrupt latch load and store machine main memory memory interface memory system microcode micron microprocessor MIPS multiply multiprocessor on-chip opcode operand operating system optional organization output page table PC relative pc+8 performance pipeline prefetch program counter race hazards register bank register file register windows result RISC CPUs RISC processors shift shifter shown in figure single specified supervisor transfer instructions transistors transputer trap unsigned virtual address VLSI window word