Digital Design Using ABELWritten by one of the original design team that produced ABEL, this a reference for users of this widely used HDL. An accompanying disk includes the ABEL compiler, optimizer and logic simulator software - allowing designers to use the HDL-based logic design techniques described. The text emphasizes solutions to common design problems, includes actual complete applications in the form of ABEL source files and corresponding design descriptions. |
Contents
Using ABEL 77 | 6 |
Combinational Circuits | 9 |
Logic Minimization | 23 |
Copyright | |
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Common terms and phrases
ABEL design ABEL source file adder AdrClr binary block Boolean equations Boolean logic buffer circuitry clock combinational comparator complement Count.q counter cube Data I/O Corporation declarations decoder described design description design file diagram Digital Design don't-care dot extension eight-bit end Figure Englewood Cliffs example Exclusive-OR feedback fitter FPGA frame grabber GenLock goto gray code header Hold implemented input conditions input variables inverted K-map language compiler latch logic circuit logic descriptions logic design logic device logic function logic gates logic minimization logic synthesis macro macrocell method minsum form minterms module multilevel multiplexer node off-set on-set optimizations output pin pin istype reg pin register pin-to-pin Prentice Hall prime implicants product terms representation reset result set of input shift register shown in Figure specified STATE_DIAGRAM StopBit2 subcube sum of products synchronous test_vectors transition logic truth table values vectors vertical blanking interval XOR gate ם ם